The present disclosure relates to a display device having a Thin Film Transistor (TFT), using an semiconductor oxide, as a drive element in a pixel, and an electronic apparatus including the display device.
In either a liquid crystal display device using an active drive system or an organic Electroluminescence (EL) display device, a thin film transistor is used as a drive element, and electric charges corresponding to a signal voltage for writing an image are held in a hold capacitor. However, when a parasitic capacitance generated in an area of intersection between a gate electrode and a source electrode or a drain electrode of the thin film transistor becomes large, there is the possibility that the signal voltage is changed and thus the image quality is caused to become worse.
In particular, in the organic EL display device, when the parasitic capacitance is large, it is also necessary to increase the capacitance value of the hold capacitor, which results in that a rate of occupation of wirings and the like in a layout of the pixels becomes large. As a result, there is caused a problem that a probability of generation of short-circuit or the like between the wirings is increased, thereby reducing the manufacturing yield.
Then, heretofore, with regard to the thin film transistor in which a semiconductor oxide such as a zinc oxide (ZnO) or an indium gallium zinc oxide (IGZO) is used in a channel, the parasitic capacitance formed in an area of intersection between a gate electrode and a source electrode or a drain electrode has been tried to be reduced.
For example, Japanese Patent Laid-Open No. 2007-220817 (referred to as Patent Document 1 hereinafter) and J. Park and 11 others: “Self-aligned top-gate amorphous gallium indium zinc oxide thin film transistors,” Applied Physics Letters, American Institute of Physics, 2008, Vol. 93, 053501 (referred to as Non-patent Document 1 hereinafter) describe a self-aligned top-gate thin film transistor. In this case, in the self-aligned top-gate thin film transistor, after a gate electrode and a gate insulating film are formed on a channel region of a semiconductor oxide thin film layer so as to have the same shape, a resistance of an area which is not covered with the gate electrode made from the semiconductor oxide thin film layer and the gate insulating film is reduced, thereby forming a source/drain region. In addition, R. Hayashi, and six others: “Improved Amorphous In—Ga—Zn—O TFTs,” SID 08 DIGEST, 2008, 42, 1, pp. 621 to 624 (referred to as Non-patent Document 2 hereinafter) describes a bottom-gate thin film transistor having a self-aligned structure. In this case, in the bottom-gate thin film transistor having the self-aligned structure, back surface exposure is carried out with a gate electrode as a mask, thereby forming both of a source region and a drain region in a semiconductor oxide film.